1. Field of the Invention
The present invention relates to a programmable controller used in a measurement control system and any other various sequence control systems and, more particularly, to a high-performance programmable controller having a simple arrangement and achieving high-speed arithmetic operations.
2. Description of the Related Art
A conventional high-performance programmable controller of this type is required to perform various operations such as logical operations in units of words, arithmetic operations, four basic and trigonometric operations using a floating point, square root operations, exponent operations, and logarithmic (LOG) operations in addition to bit operations. As a result, a designer has a difficult objective to satisfy the above needs with economical and dimensional limitations. Various implementations have been proposed from these points of view.
A typical conventional programmable controller will be described with reference to FIG. 1. In this controller, a bus line 1 is connected to a bit processor 2 for bit operations, which includes gate arrays for performing high-speed bit operations such as ladder chart processing having a large number of processing steps, a microprocessor 3 for executing operations in units of words, which cannot be performed by the bit processor 2, a coprocessor 4 for executing floating-point processing, a code memory 5 for storing each instruction code data, an instruction processing program memory 6 for storing the processing routine of each instruction, a data memory 7 for storing processing data and processed data, a process input/output circuit (PIO) 8, and the like. An output from the bit processor 2 is input to the microprocessor 3 through a signal line 9.
In the controller having the arrangement described above, when the bit processor 2 sequentially reads out instructions from the code memory 5, the bit processor 2 reads out the processing routine for each instruction from the instruction processing program memory 6 to execute a bit operation. In this bit operation in units of words, the bit processor 2 reads out bit data from the data memory 7 and the process input/output circuit (PIO) 8 to perform the bit operation. At the same time, the processed data is written in the data memory 7 and the process input/output circuit (PIO) 8.
When the bit processor 2 reads out an operation instruction to be performed in units of words but not to be performed by the bit processor 2 from the code memory 5, the bit processor 2 outputs an interrupt signal through the signal line 9 to inform the operation disable state to the microprocessor 3. When the microprocessor 3 receives this interrupt signal, the microprocessor 3 issues an INTA signal twice, which operation is the standard procedure of an Intel microprocessor, thereby recognizing the content of the interrupt signal. Thereafter, the microprocessor 3 reads out the instruction from the bit processor 2 and decodes the instruction on the basis of the recognized content of the interrupt signal. The microprocessor 3 reads out the processing routine corresponding to the decoded instruction from the instruction processing program memory 6, and fetches the data from the data memory 7 and the process input/output circuit (PIO) 8, thereby performing processing in units of words. When the operation in units of words is completed in the microprocessor 3, the microprocessor 3 informs the end of processing to the bit processor 2. The bit processor 2 then executes the next bit operation.
When the microprocessor 3 determines that an instruction involves floating-point processing which is inefficient processing for the microprocessor 3, the microprocessor 3 informs it to the floating-point operation coprocessor 4. The floating-point operation function is then shifted to the coprocessor 4. At this time, the microprocessor 3 transfers its control to the coprocessor 4 after the microprocessor 3 prepares data to be processed by the coprocessor 4. At the same time, the microprocessor 3 also transfers the content of processed data to the coprocessor 4.
The coprocessor 4 reads out the processing routine for the instruction processing program memory 6 and executes the floating-point operation and sends the processing result to the microprocessor 3. After the microprocessor 3 receives the processed data from the coprocessor 4, the microprocessor 3 outputs this processed data to the data memory 7 and the process input/output circuit (PIO) 8. The microprocessor 3 informs the end of operation for the floating-point instruction to the bit processor 2. The bit processor 2 reads out the next instruction and executes the operation in the same procedures as described above.
Although the above programmable controller can be realized at a relatively low cost, the following problems are posed.
(1) Although high-speed processing can be performed by the bit processor 2 in a bit operation, the operation function must be shifted to the microprocessor 3 in word operations in units of words. As a result, much time is required for data communication and prescribed control processing. Therefore, high-speed processing cannot be achieved even if the microprocessor 3 is used. PA1 (2) In particular, in a floating-point operation, the processing route must be shifted in an order of the bit processor 2, the microprocessor 3, and the coprocessor 4. Therefore, even if the high-speed coprocessor 4 is used, its performance cannot be sufficiently exhibited. PA1 (3) Since the conventional programmable controller has the three processors 2, 3, and 4, a large space is required for data communication buffer ICs and interconnections, thereby limiting the processing speed. PA1 (4) In general, of all the functions of the programmable controller, the double-length floating-point operation function of the coprocessor 4 and the virtual memory function of the microprocessor 3 are often unnecessary. Although these functions can be omitted to achieve operations at a higher speed, LSIs of this type are often general-purpose products and cannot sufficiently cope with the above requirement. PA1 (5) The parity check function and the reexecution function upon occurrence of an error (reliability, availability, and serviceability) are insufficient because the microprocessor 3 does not have these functions. PA1 (6) Since the microprocessor 3 executes each instruction while decoding it, i.e. interpreter method, the processing speed becomes low due to the specific arrangement of the programmable controller for the reason to be described as follows. In a programmable controller, a program is read out from a memory by a program loader and is set displayable, and the program can be modified even during operation. Therefore, unlike, for example, a computer, a program cannot be compiled to translate it into a compact machine language. PA1 (7) New demand has recently arisen for most advanced processing such as an SFC (Sequential Function Chart) complying with the IEC (International Electrotechnical Commission) standards as the international standards of programmable controllers and a fuzzy function at high speed without increasing the cost. The microprocessor 3 cannot sufficiently cope with the above demand. PA1 (8) In addition, the microprocessor 3 performs interrupt processing when an overflow occurs in the operation result, thus prolonging the processing time. In order to eliminate this drawback, the interrupt processing may be omitted. In this case, however, since an overflow in status data must always be checked, it takes much time. PA1 (1) a programmable controller in which an instruction system is systematized to simplify the hardware arrangement and achieve high-speed operations; PA1 (2) a programmable controller in which a plurality of main circuits are realized on a single chip, and word operations and floating-point operations can be executed at high speed as in bit operations; PA1 (3) a programmable controller which employs an SFC complying with the IEC standards as the international programmable controller standards to achieve most advanced operations at high speed and low cost; PA1 (4) a programmable controller which realizes an RAS function for assuring reexecution during a parity check required as the controller and upon occurrence of a memory error; and PA1 (5) a programmable controller capable of performing interface processing with a program loader within a short period of time.
The programmable controller has the above various problems. The importance of cost performance must be recognized while maintaining high performance. On the other hand, when a large number of ICs are used, problems are posed as to the cost, reliability, and mounting space, although the resultant arrangement may have high performance. A combination of a commercially available LSI and a gate array is a popular technique in view of cost performance.
Since recent technical advances set out a silicon compiler or a standard cell technique capable of relatively easily designing a customized LSI within a short period of time and easily manufacturing a gate array, technical environments associated with such a technique are subject to spontaneous changes. That is, a high integration density of the gate array, which cannot be conventionally achieved, can be easily realized. In this case, however, only a limited number of circuits are mounted on one chip. It is very difficult to mount the three processors 2, 3, and 4 shown in FIG. 1 on one chip without any modifications in view of integration density. Although a specific circuit arrangement to be mounted on one chip and realization of high performance are current issues, no practical application is yet found.